HARFLOW3D: A Latency-Oriented 3D-CNN Accelerator Toolflow for HAR on FPGA Devices
Authors: Petros Toupas, Alexander Montgomerie-Corcoran, Christos-Savvas Bouganis, Dimitrios Tzovaras
AI-generated Key Points
- 3D Convolutional Neural Networks (CNNs) are effective for Human Action Recognition (HAR) tasks
- However, they require more computational and memory resources than 2D CNNs due to the additional temporal dimension
- HARFLOW3D is a novel toolflow that maps 3D CNN models onto Field Programmable Gate Array (FPGA) devices while considering the model's inherent characteristics and the features of the targeted FPGA device
- The toolflow takes as input a 3D CNN in ONNX format and a description of the FPGA characteristics, generating a design that minimizes computation latency
- It comprises several parts, including a 3D CNN parser, performance and resource model, scheduling algorithm for executing 3D models on generated hardware, resource-aware optimization engine tailored for 3D models, and automated mapping to synthesizable code for FPGAs
- Experiments showed that HARFLOW3D can support a broad range of models and devices with high-performing results compared to existing hand-tuned approaches
- HARFLOW3D was able to achieve up to five times better performance compared to some existing hand-tuned approaches
- There is an increasing need for efficient tools like HARFLOW3D that can accelerate computations involving volumetric data using FPGAs in video-related applications such as video surveillance, autonomous driving and patient monitoring.
Abstract: For Human Action Recognition tasks (HAR), 3D Convolutional Neural Networks have proven to be highly effective, achieving state-of-the-art results. This study introduces a novel streaming architecture based toolflow for mapping such models onto FPGAs considering the model's inherent characteristics and the features of the targeted FPGA device. The HARFLOW3D toolflow takes as input a 3D CNN in ONNX format and a description of the FPGA characteristics, generating a design that minimizes the latency of the computation. The toolflow is comprised of a number of parts, including i) a 3D CNN parser, ii) a performance and resource model, iii) a scheduling algorithm for executing 3D models on the generated hardware, iv) a resource-aware optimization engine tailored for 3D models, v) an automated mapping to synthesizable code for FPGAs. The ability of the toolflow to support a broad range of models and devices is shown through a number of experiments on various 3D CNN and FPGA system pairs. Furthermore, the toolflow has produced high-performing results for 3D CNN models that have not been mapped to FPGAs before, demonstrating the potential of FPGA-based systems in this space. Overall, HARFLOW3D has demonstrated its ability to deliver competitive latency compared to a range of state-of-the-art hand-tuned approaches being able to achieve up to 5$\times$ better performance compared to some of the existing works.
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