Search Results for « Decimal multiplication »

There are two primary ways to think about how to multiply decimals. Both of these ways are demonstrated step by step above. The first method is called estimation. Begin by writing out your original problem. Once you have done this remove the decimal from the original numbers and multiply them. Then round any decimal numbers and multiply again. The final step is to place a decimal back into the a;

There are two primary ways to think about how to multiply decimals. Both of these ways are demonstrated step by step above. The first method is called estimation. Begin by writing out your original problem. Once you have done this remove the decimal from the original numbers and multiply them. Then round any decimal numbers and multiply again. The final step is to place a decimal back into the a;

Decimal multiplication is the task of multiplying two numbers in base $10^N.$ Specifically, we focus on the number-theoretic transform (NTT) family of algorithms. Using only portable techniques, we achieve a 3x-5x speedup over the mpdecimal library. In this paper we describe our implementation and discuss further possible optimizations. We also present a simple cache-efficient algorithm for in-place $2n \times n$ or $n \times 2n$ matrix transposition, the need for which arises in the "six-step algorithm" variation of the matrix Fourier algorithm, and which does not seem to be widely known. Another finding is that use of two prime moduli instead of three makes sense even considering the worst case of increasing the size of the input, and makes for simpler answer recovery.

Financial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal multiplication is found in most decimal-based applications and so its optimized design is very important for fast execution. In this paper two new parallel decimal multipliers in FPGA are proposed. These are based on a new decimal adder/subtractor also proposed in this paper. The new decimal multipliers improve state-of-the-art parallel decimal multipliers. Compared to previous architectures, implementation results show that the proposed multipliers achieve 26% better area and 12% better performance. Also, the new decimal multipliers reduce the area and performance gap to binary multipliers and are smaller for 32 digit operands.

Decimal arithmetic using software is slow for very large-scale applications. On the other hand, when hardware is employed, extra area overhead is required. A balanced strategy can overcome both issues. Our proposed methods are compliant with the IEEE 754-2008 standard for decimal floating-point arithmetic and combinations of software and hardware. In our methods, software with some area-efficient decimal component (hardware) is used to design the multiplication process. Analysis in a RISC-V-based integrated co-design evaluation framework reveals that the proposed methods provide several Pareto points for decimal multiplication solutions. The total execution process is sped up by 1.43× to 2.37× compared with a full software solution. In addition, 7–97% less hardware is required compared with an area-efficient full hardware solution.

This study examined 11 U.S. textbooks written for prospective teachers to investigate how standard decimal multiplication and division algorithms are presented, especially the rationale of both algorithms. Analytical frameworks of various methods used in different textbooks were developed. The findings suggest that half of the textbooks do not fully present the standard algorithms. The results indicate variations in textbooks’ explanations for the procedures involved in the standard algorithms. Some procedures are explained more frequently than others. The reason why moving the decimal point in both dividend and divisor keeps the quotient unchanged is provided in most of the textbooks. Half of the textbooks explain why adding the decimal places in the multiplication algorithm. However, only two books explain the rationale for placing the decimal point in the quotient. The findings suggest that textbook writers pay more attention to explaining the rationales of the standard algorithms for decimal multiplication and division.

The objective of this work is to implement a scalable decimal to binary converter from 8 to 64 bits (i.e 2-digit to 16-digit) using parallel architecture. The proposed converters, along with binary coded decimal (BCD) adder and binary to BCD converters, are used in parallel implementation of Urdhva Triyakbhyam (UT)-based 32-bit BCD multiplier. To increase the performance, compressor circuits were used in converters and multiplier. The designed hardware circuits were verified by behavioural and post layout simulations. The implementation was carried out using Virtex-6 Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) with 90-nm technology library platforms. The results on FPGA shows that compressor based converters and multipliers produced less amount of propagation delay with a slight increase of hardware resources. In case of ASIC implementation, a compressor based converter delay is equivalent to conventional converter with a slight increase of gate count. However, the reduction of delay is evident in case of compressor based multiplier.

Reversible logic gates under ideal conditions produce zero power dissipation.This factor highlights the usage of these gates in optical computing, low power CMOS design, quantum optics and quantum computing.The growth of decimal arithmetic in various applications as stressed the need to propose the study on reversible binary to BCD converter which plays a greater role in decimal multiplication for providing faster results.The different parameters such as gate count,garbage output and constant input are more optimized in the proposed fixed bit binary to binary coded decimal converter than the existing design.