First hardware demonstration of a continuous-state probabilistic computer with programmable energy-defined sampling
Chao Fang, Hsuan Yao Tu, Yihan He, Xiao Gong, Chin-Fu Nien, Gengchiau Liang · arXiv: 2610.31339v1 · Summary page
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A probabilistic computer moves beyond binary choices
Probabilistic computers search by making controlled random choices. This hardware demonstration extends that idea from binary units to bounded, continuous-valued variables, represented at finite precision on an FPGA. Each unit samples from a conditional distribution defined by a local energy, while random-number generation is kept separate from the sampling rule. That separation could allow future implementations to use physical sources of randomness with different native distributions.
The prototype tackled factorization and recovered stored MNIST patterns without pretrained networks; a software version explored feasible solution regions. For the tested 7-bit factorization case, the FPGA reduced mean core solving time approximately 33,000-fold relative to the evaluated quadratic unconstrained binary optimization software implementation. This is an intriguing demonstration of a different computing primitive, not yet a general speed advantage: the striking comparison concerns a small problem and a particular software baseline.
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