Résultats de recherche pour « Decimal multiplication »

We give a~detailed construction of the complete ordered field of real numbers by means of infinite decimal expansions. We prove that in the canonical encoding of decimals neither addition nor multiplication is {\em computable}, but that both operations are {\em weakly computable}; we introduce both kinds of computability in greater generality. We determine which additive and multiplicative shifts (restrictions of addition and multiplication to one variable) are computable, and prove that each of these shifts becomes computable after a~permutation of encoding. We ask if it is the case for the bivariate addition and multiplication.

Financial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal multiplication is found in most decimal-based applications and so its optimized design is very important for fast execution. In this paper two new parallel decimal multipliers in FPGA are proposed. These are based on a new decimal adder/subtractor also proposed in this paper. The new decimal multipliers improve state-of-the-art parallel decimal multipliers. Compared to previous architectures, implementation results show that the proposed multipliers achieve 26% better area and 12% better performance. Also, the new decimal multipliers reduce the area and performance gap to binary multipliers and are smaller for 32 digit operands.

The BCD (Binary Coded Decimal) being the more accurate and human-readable representation with ease of conversion, is prevailing in the computing and electronic communication.In this paper, a tree-structured parallel BCD addition algorithm is proposed with the reduced time complexity. BCD adder is more effective with a LUT (Look-Up Table)-based design, due to FPGA (Field Programmable Gate Array) technology's enumerable benefits and applications. A size-minimal and depth-minimal LUT-based BCD adder circuit construction is the main contribution of this paper.

Decimal arithmetic using software is slow for very large-scale applications. On the other hand, when hardware is employed, extra area overhead is required. A balanced strategy can overcome both issues. Our proposed methods are compliant with the IEEE 754-2008 standard for decimal floating-point arithmetic and combinations of software and hardware. In our methods, software with some area-efficient decimal component (hardware) is used to design the multiplication process. Analysis in a RISC-V-based integrated co-design evaluation framework reveals that the proposed methods provide several Pareto points for decimal multiplication solutions. The total execution process is sped up by 1.43× to 2.37× compared with a full software solution. In addition, 7–97% less hardware is required compared with an area-efficient full hardware solution.

Decimal multiplication is the task of multiplying two numbers in base $10^N.$ Specifically, we focus on the number-theoretic transform (NTT) family of algorithms. Using only portable techniques, we achieve a 3x-5x speedup over the mpdecimal library. In this paper we describe our implementation and discuss further possible optimizations. We also present a simple cache-efficient algorithm for in-place $2n \times n$ or $n \times 2n$ matrix transposition, the need for which arises in the "six-step algorithm" variation of the matrix Fourier algorithm, and which does not seem to be widely known. Another finding is that use of two prime moduli instead of three makes sense even considering the worst case of increasing the size of the input, and makes for simpler answer recovery.

This paper investigates the length of the repeating decimal part when a fraction is expressed in decimal form. First, it provides a detailed explanation of how to calculate the length of the repeating decimal when the denominator of the fraction is a power of a prime number. Then, by factorizing the denominator into its prime factors and determining the repeating decimal length for each prime factor, the paper concludes that the overall repeating decimal length is the least common multiple of these lengths. Furthermore, it examines the conditions under which the repeating decimal length equals the denominator minus 1 and discusses whether such fractions exist in infinite quantity. This topic is connected to an unsolved problem posed by Gauss in the 18th century and is also closely related to the important question of whether cyclic numbers exist in infinite quantity.