# Design and implementation of a synchronous Hardware Performance Monitor for a RISC-V space-oriented processor

**Authors:** Miguel Jiménez Arribas, Agustín Martínez Hellín, Manuel Prieto Mateo, Iván Gamino del Río, Andrea Fernandez Gallego, Oscar Rodríguez Polo, Antonio da Silva, Pablo Parra, Sebastián Sánchez  
**arXiv:** [2404.05389](https://arxiv.org/abs/2404.05389)  
**Date:** 2024-04-08  
**Summary page:** https://www.summarizepaper.com/en/paper/2404.05389v1/

## Key points

- Development and implementation of a Performance Measurement Unit (PMU) for a RISC-V On-Board Computer designed for space applications
- Importance of collecting statistics about program execution within a CPU, especially in safety-critical software systems where timing performance is crucial
- Novel approach to monitoring techniques synchronizes events triggered with executed instructions rather than counting them immediately
- Design of the PMU involves adding statistical counters to an existing pipelined RISC-V processor to ensure event counting aligns with instruction execution
- Validation of the design by calculating events triggered by various programs and executing them on the on-board computer, demonstrating accurate operation of the PMU
- Ability to support new events during development, showcasing the extensibility of the PMU with minimal time and cost
- Porting benchmarks such as CoreMark and Dhrystone to the platform for comparison with external references, confirming correct behavior of the proposed HPM
- Future enhancements include exploring new ways to extract synchronized event data and improving processor performance

## Summary

In this paper, we present the development and implementation of a Performance Measurement Unit (PMU) for a RISC-V On-Board Computer designed for space applications. The importance of collecting statistics about program execution within a CPU is highlighted, especially in safety-critical software systems where timing performance is crucial. Our novel approach to monitoring techniques synchronizes events triggered with executed instructions rather than counting them immediately. The design of the PMU involves adding statistical counters to an existing pipelined RISC-V processor, ensuring that event counting aligns with instruction execution. We validate our design by calculating events triggered by various programs and executing them on the on-board computer, demonstrating accurate operation of the PMU. Additionally, we test the ability to support new events during development, showcasing the extensibility of the PMU with minimal time and cost. Furthermore, we port benchmarks such as CoreMark and Dhrystone to our platform for comparison with external references, confirming the correct behavior of our proposed HPM. Future enhancements include exploring new ways to extract synchronized event data and improving processor performance. This work has been supported by predoctoral aids from European Social Fund (ESF) and Spanish Ministerio de Ciencia, Innovación y Universidades (MCIN), along with funding from projects related to Solar Orbiter mission. The authors declare no competing financial interests or personal relationships influencing their work reported in this paper. Data availability is ensured upon request.