# VeriBug: An Attention-based Framework for Bug-Localization in Hardware Designs

**Authors:** Giuseppe Stracquadanio, Sourav Medya, Stefano Quer, Debjit Pal  
**arXiv:** [2401.09494](https://arxiv.org/abs/2401.09494)  
**Date:** 2024-01-17  
**Summary page:** https://www.summarizepaper.com/en/paper/2401.09494v1/

## Key points

- System-on-Chip designs have become more complex and larger in recent years, leading to a higher risk of undetected bugs with serious consequences.
- Debugging and verification processes in hardware design are further complicated by tight time-to-market deadlines and the need to produce a large number of devices.
- VeriBug is a novel bug-localization technique that uses deep learning to accelerate debugging at the Register-Transfer Level by generating explanations for likely root causes of bugs.
- The architecture of VeriBug includes three key components: Feature extraction, Deep learning model, and Explanation generation.
- VeriBug extracts features from input designs using GOLDMINE to generate Control Data Flow Graphs (CDFGs) and Variable Dependency Graphs (VDGs, performs dependence analysis, applies design slicing, and learns execution semantics with a deep-learning architecture to localize bugs without relying on specific code characteristics or extensive labeled datasets.

## Summary

In recent years, the complexity and size of System-on-Chip designs have been rapidly increasing. This has led to a greater risk of undetected bugs that could result in significant consequences such as property damage or loss of life. The pressure to meet tight time-to-market deadlines and produce a large number of devices further complicates the debugging and verification process in hardware design. Despite extensive research in simulation and formal methods, debugging remains a time-consuming and resource-intensive task. To address these challenges, a novel bug-localization technique called VeriBug has been proposed. VeriBug leverages deep learning to accelerate debugging at the Register-Transfer Level by generating explanations for likely root causes of bugs. The architecture of VeriBug consists of three key components: Feature extraction, Deep learning model, and Explanation generation. The Feature extraction component extracts features from the input design using GOLDMINE to generate Control Data Flow Graphs (CDFGs) and Variable Dependency Graphs (VDGs). Dependence analysis is performed on the VDG to identify control and data dependencies for target variables. Design slicing is then applied to extract relevant statements based on the identified dependencies. VeriBug overcomes limitations seen in software-based bug detection techniques by automatically learning features from Abstract Syntax Trees (ASTs) at lower abstraction levels. This design-agnostic approach allows VeriBug to generalize across different designs without requiring retraining. By learning execution semantics with a deep-learning architecture, VeriBug can localize bugs by comparing learned semantics from failure and correct simulation traces. One of the key contributions of VeriBug is its ability to localize bugs in hardware designs without relying on specific code characteristics or building extensive datasets with labeled programs containing bugs. The approach taken by VeriBug is fully integratable with existing verification workflows without additional time or resources. Overall, VeriBug represents a significant advancement in bug localization for hardware designs, offering a more efficient and effective solution for identifying potential issues in complex System-on-Chip designs.