# An Implementation of a Dual-Processor System on FPGA

**Authors:** Mohammed Eqbal Eshaq  
**arXiv:** [2302.08322](https://arxiv.org/abs/2302.08322)  
**Date:** 2023-02-15  
**Summary page:** https://www.summarizepaper.com/en/paper/2302.08322v2/

## Key points

- Proposal of a tightly-coupled FPGA-based dual-processor platform
- Utilization of FPGA resources optimization
- Creation of a general-purpose system to accommodate modern application processing trends
- Use of Nios II 32-bit embedded soft-core processor architecture for Altera Cyclone III FPGAs
- Introduction highlighting the problem statement and rising demand for combined general-purpose and processing capabilities
- Background information on FPGA technology, specifically Altera family of FPGAs and Quratus II platform
- Discussion on SoPC builder, soft-hardware components, and Nios II processor
- Literature review exploring multiprocessor systems on multiple chips and MPSoC architectures
- System design overview and testing strategy in Chapter 2
- Results and discussion from experiments conducted on uniprocessor and dual-processor systems in Chapter 3
- Analysis of resource usage and comparisons with industry-standard CPU platforms
- Conclusion summarizing key findings, success in optimizing FPGA resources through dual-processor platform
- Future work and recommendations for further research and development in Chapter 5

## Summary

This work proposes a design and implementation of a tightly-coupled FPGA-based dual-processor platform that optimizes the utilization of FPGA resources. The goal is to create a system that is general-purpose and can accommodate current trends in application processing. The proposed prototype utilizes the Nios II 32-bit embedded soft-core processor architecture designed for the Altera Cyclone III family of FPGAs. The study begins with an introduction that highlights the problem statement, which is the rising demand for a system that combines general-purpose capabilities with processing abilities to handle modern applications. The background information on FPGA technology provides an overview of the Altera family of FPGAs, specifically focusing on the Cyclone FPGA and the Quratus II platform. The SoPC builder and soft-hardware components are also discussed, along with an explanation of the Nios II processor. A literature review and related work section explores multiprocessor systems on multiple chips and multiprocessor system-on-chip (MPSoC) architectures. This sets the foundation for the proposed system design and testing strategy outlined in Chapter 2. The design overview covers system components, while the testing strategy explains how experiments will be conducted to evaluate performance. Chapter 3 presents results and discussion from two experiments conducted on different configurations of a uniprocessor and a dual-processor system. Resource usage is analyzed, and conclusions are drawn based on benchmark results. Additionally, comparisons are made against published results for common industry-standard CPU platforms. The conclusion chapter summarizes key findings from the study, highlighting the success of optimizing FPGA resources through the proposed dual-processor platform. Future work and recommendations are provided in Chapter 5, suggesting areas for further research and development. In summary, this work focuses on designing and implementing a tightly-coupled FPGA-based dual-processor platform that addresses the increasing demand for general-purpose systems capable of handling modern application processing trends. Through experimentation and evaluation, it demonstrates optimized resource utilization and compares performance against industry standard CPU platforms utilizing Nios II processor architecture designed for Altera Cyclone III FPGAs.