# LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications

**Authors:** Yaman Umuroglu, Yash Akhauri, Nicholas J. Fraser, Michaela Blott  
**arXiv:** [2004.03021](https://arxiv.org/abs/2004.03021)  
**Date:** 2020-04-06  
**Summary page:** https://www.summarizepaper.com/en/arxiv-id/2004.03021v1/

## Key points

- LogicNets is a method for designing neural network topologies that can be mapped to an efficient FPGA implementation.
- It addresses the challenge of deploying deep neural networks for applications with high throughput or low latency requirements.
- The key innovation of LogicNets is exploiting the equivalence between artificial neurons and quantized inputs/outputs and truth tables.
- By training quantized neural networks, they can be converted to a netlist of truth tables and deployed as a pipelinable, massively parallel FPGA circuit.
- To obtain smaller networks that fit onto one FPGA chip, LogicNets uses a fan-in driven hardware cost model to guide topology design and combines sparsity with low-bit activation quantization to limit neuron fan-in.
- The authors behind LogicNets are Yaman Umuroglu, Yash Akhauri, Nicholas J. Fraser, and Michaela Blott.
- Evaluations on two tasks in high-energy physics and network intrusion detection show that combining sparsity with low-bit activation quantization results in circuits with small logic depth and low LUT cost while achieving competitive accuracy with less than 15 ns inference latency and hundreds of millions of inferences per second throughput.

## Summary

LogicNets is a novel method for designing neural network topologies that can be directly mapped to a highly efficient FPGA implementation. This approach addresses the computational challenge of deploying deep neural networks for applications with high throughput or low latency requirements. The key innovation of LogicNets lies in exploiting the equivalence between artificial neurons and quantized inputs/outputs and truth tables. By training quantized neural networks, they can be converted to a netlist of truth tables and deployed as a pipelinable, massively parallel FPGA circuit. To obtain smaller networks that fit onto one FPGA chip, LogicNets uses a fan-in driven hardware cost model to guide topology design and combines sparsity with low-bit activation quantization to limit neuron fan-in. The authors behind LogicNets are Yaman Umuroglu, Yash Akhauri, Nicholas J. Fraser, and Michaela Blott. Their paper titled "LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications" presents an innovative solution to address the challenges associated with deploying deep neural networks for applications that require very high throughput or extremely low latency. Evaluations on two tasks with very high intrinsic throughput requirements in high-energy physics and network intrusion detection show that combining sparsity with low-bit activation quantization results in circuits with small logic depth and low LUT cost while achieving competitive accuracy with less than 15 ns inference latency and hundreds of millions of inferences per second throughput.