# UVM Based Reusable Verification IP for Wishbone Compliant SPI Master Core

**Authors:** Lakhan Shiva Kamireddy, Lakhan Saiteja Kamireddy  
**arXiv:** [1809.10845](https://arxiv.org/abs/1809.10845)  
**Date:** 2018-09-28  
**Summary page:** https://www.summarizepaper.com/en/paper/1809.10845v1/

## Key points

- The System on Chip design industry heavily relies on functional verification to ensure bug-free designs.
- Effective verification is crucial as engineers develop increasingly dense chips with advanced functionality.
- Authors Lakhan Shiva Kamireddy and Lakhan Saiteja Kamireddy present a methodology for verifying a wishbone compliant SPI Master core using UVM based on System Verilog.
- The authors successfully verified an SPI Master IP core design that is wishbone compliant and compatible with the SPI protocol and bus.
- Simulations and waveform analysis were conducted using QuestaSim, while coverage analysis was performed using Integrated Metrics Center from Cadence.
- The methodology showcased in the paper ensures the reliability of the system through detailed verification results.
- Future directions proposed by the authors aim to develop even more reliable systems in functional verification for System on Chip designs, contributing to advancing modern verification techniques.

## Summary

The System on Chip design industry heavily relies on functional verification to ensure bug-free designs. As engineers develop increasingly dense chips with advanced functionality, the need for effective verification becomes even more crucial. In their paper titled "UVM Based Reusable Verification IP for Wishbone Compliant SPI Master Core," authors Lakhan Shiva Kamireddy and Lakhan Saiteja Kamireddy present a robust methodology for verifying a wishbone compliant Serial Peripheral Interface (SPI) Master core using the Universal Verification Methodology (UVM) based on System Verilog. By utilizing the UVM factory pattern with parameterized classes, they aim to create a reusable and reliable verification IP for SPI, a full duplex communication protocol commonly used in embedded systems. The authors successfully verified an SPI Master IP core design that is wishbone compliant and compatible with the SPI protocol and bus. They conducted simulations and waveform analysis using QuestaSim, while coverage analysis was performed using Integrated Metrics Center from Cadence. The results of their verification process were detailed in the paper, showcasing the effectiveness of their methodology in ensuring the reliability of the system. Furthermore, the authors proposed future directions for their work, suggesting avenues for developing even more reliable systems in the field of functional verification for System on Chip designs. This research contributes to advancing modern verification techniques in response to the growing complexity of chip designs, ultimately enhancing the quality and performance of integrated circuits in various applications.