# Design Guidelines for High-Performance SCM Hierarchies

**Authors:** Dmitrii Ustiugov, Alexandros Daglis, Javier Picorel, Mark Sutherland, Edouard Bugnion, Babak Falsafi, Dionisios Pnevmatikatos  
**arXiv:** [1801.06726](https://arxiv.org/abs/1801.06726)  
**Date:** 2018-01-20  
**Summary page:** https://www.summarizepaper.com/en/paper/1801.06726v4/

## Key points

- Integration of emerging storage-class memory (SCM) in servers to improve performance and cost compared to DRAM-only architectures
- SCM offers high density and access latencies similar to DRAM but higher memory access latency poses challenges for latency-sensitive services
- Proposal of deploying a modestly sized high-bandwidth 3D stacked DRAM cache in an SCM-mostly memory system to mitigate latency issues
- Identification of key design parameters in the memory hierarchy that impact performance and cost when combining SCM with a 3D stacked DRAM cache
- Introduction of a methodology for provisioning these parameters based on a target performance/cost goal
- Demonstration using PCM as a case study, showing that a two bits/cell technology achieves a performance/cost sweet spot, reducing memory subsystem cost by 40% while maintaining performance within 3% of the best performing DRAM-only system
- Valuable insights into designing high-performance SCM hierarchies in servers and guidelines for integrating SCM effectively while considering cost constraints
- Contribution to advancing the adoption of emerging SCM technologies in server architectures.

## Summary

This paper explores the integration of emerging storage-class memory (SCM) in servers to improve overall performance and cost compared to existing DRAM-only architectures. SCM offers high density and access latencies similar to DRAM but its higher memory access latency poses challenges for latency-sensitive memory-resident services. To mitigate this, the authors propose deploying a modestly sized high-bandwidth 3D stacked DRAM cache in an SCM-mostly memory system. The paper identifies key design parameters in the memory hierarchy that impact performance and cost when combining SCM technology with a 3D stacked DRAM cache. A methodology is introduced to drive provisioning for each of these parameters based on a target performance/cost goal. Using PCM as a case study, the authors demonstrate that a two bits/cell technology achieves a performance/cost sweet spot, reducing the memory subsystem cost by 40% while maintaining performance within 3% of the best performing DRAM-only system. This research provides valuable insights into designing high-performance SCM hierarchies in servers, offering guidelines for integrating SCM effectively and optimizing performance while considering cost constraints. The findings contribute to advancing the adoption of emerging SCM technologies in server architectures.