# TOT Measurement Implemented in FPGA TDC

**Authors:** Huanhuan Fan, Ping Cao, Shubin Liu, Qi An  
**arXiv:** [1501.06846](https://arxiv.org/abs/1501.06846)  
**Date:** 2015-01-26  
**Summary page:** https://www.summarizepaper.com/en/paper/1501.06846v1/

## Key points

- Time measurement is critical for particle identification in high energy physical experiments
- Modern time measurement systems must meet high resolution specifications and maintain high integrity
- Field Programmable Gate Array (FPGA) time-to-digital converters (TDCs) have become a mature and prominent method for time measurement due to their ability to provide excellent resolution and accuracy
- To correct the time-walk effect caused by leading timing, it is necessary to include time-over-threshold (TOT) measurement in FPGA TDCs
- Traditional TDCs can only recognize one type of signal edge - either leading or trailing - requiring two TDC channels to measure the interval accurately, which increases resource consumption and reduces integrity
- A new method of TOT measurement implemented in a Xilinx Virtex-5 FPGA achieves accurate results using only one input channel while maintaining resource consumption, time resolution, and integrity guarantees
- The TDC can achieve resolutions better than 15 ps for leading edge measurements and 37 ps for TOT measurements with a measuring dead time of about 2 clock cycles, making it suitable for applications with higher physical event rates.
- This research demonstrates an innovative approach to improving TOT measurement in FPGA-based systems that could have significant implications for future particle identification experiments requiring highly accurate timing information.

## Summary

In high energy physical experiments, time measurement is a critical factor for particle identification. With the advancement of physical goals and electronics, modern time measurement systems must meet high resolution specifications and maintain high integrity. In recent years, Field Programmable Gate Array (FPGA) time-to-digital converters (TDCs) have become a mature and prominent method for time measurement due to their ability to provide excellent resolution and accuracy. To correct the time-walk effect caused by leading timing, it is necessary to include time-over-threshold (TOT) measurement in FPGA TDCs. TOT can be obtained by measuring the interval between signal leading and trailing edges. However, traditional TDCs can only recognize one type of signal edge - either leading or trailing. To measure the interval accurately, two TDC channels are typically used simultaneously - one for leading and one for trailing. Unfortunately, this approach increases the amount of FPGA resources required and reduces the TDC's integrity. This paper presents a new method of TOT measurement implemented in a Xilinx Virtex-5 FPGA that achieves accurate results using only one input channel. The method ensures both consumed resources and time resolution are guaranteed while maintaining high integrity. Test results show that this TDC can achieve resolutions better than 15 ps for leading edge measurements and 37 ps for TOT measurements with a measuring dead time of about 2 clock cycles. This makes it suitable for applications with higher physical event rates. Overall, this research demonstrates an innovative approach to improving TOT measurement in FPGA-based systems that could have significant implications for future particle identification experiments requiring highly accurate timing information.