# Design and Performance Analysis of hybrid adders for high speed arithmetic circuit

**Authors:** Rajkumar Sarma, Veerati Raju  
**arXiv:** [1207.2840](https://arxiv.org/abs/1207.2840)  
**Date:** 2012-07-12  
**Summary page:** https://www.summarizepaper.com/en/paper/1207.2840v1/

## Key points

- The paper presents the design and performance analysis of hybrid adders for high-speed arithmetic circuits.
- Two techniques are focused on: Gate Diffusion Technique (GDI) and Pass Transistor Logic (PTL-GDI).
- GDI technique reduces power consumption, propagation delay, and power delay product (PDP) by eliminating redundant transistors in logic gates.
- PTL reduces the count of transistors used in logic gates.
- Two new designs based on GDI and PTL techniques are proposed, which are more power-efficient compared to existing design techniques.
- Both designs use only 10 transistors to implement SUM and CARRY functions in a cascaded manner with an XOR cell as input for both SUM and CARRY cells.
- In the proposed GDI adder design, both SUM and CARRY cells are designed using GDI technique.
- In the proposed PTL-GDI adder design, the SUM cell is constructed using PTL technique while the CARRY cell is designed using GDI technique.
- The advantages of both designs are discussed in detail along with simulation results obtained from Cadence Virtuoso 180nm environment to substantiate their significance.
- The paper contributes to improving power efficiency in arithmetic circuits through innovative adder designs based on GDI and PTL techniques with performance analysis providing valuable insights into their effectiveness compared to existing hybrid adders.

## Summary

This paper presents the design and performance analysis of hybrid adders for high-speed arithmetic circuits. The authors focus on two techniques: Gate Diffusion Technique (GDI) and Pass Transistor Logic (PTL-GDI). The GDI technique is used to reduce power consumption, propagation delay, and power delay product (PDP) by eliminating redundant transistors in different logic gates. On the other hand, PTL reduces the count of transistors used in logic gates. The paper proposes two new designs based on GDI and PTL techniques which are found to be more power-efficient compared to existing design techniques. Both designs use only 10 transistors to implement the SUM and CARRY functions in a cascaded manner with an XOR cell as input for both SUM and CARRY cells. In the proposed GDI adder design, both the SUM and CARRY cells are designed using GDI technique while in the proposed PTL-GDI adder design, the SUM cell is constructed using PTL technique while the CARRY cell is designed using GDI technique. The advantages of both designs are discussed in detail along with simulation results obtained from Cadence Virtuoso 180nm environment to substantiate their significance. This paper contributes to improving power efficiency in arithmetic circuits through innovative adder designs based on GDI and PTL techniques with performance analysis providing valuable insights into their effectiveness compared to existing hybrid adders.