# FPGA Architecture for Multi-Style Asynchronous Logic

**Authors:** N. Huot, H. Dubreuil, L. Fesquet, M. Renaudin  
**arXiv:** [0710.4711](https://arxiv.org/abs/0710.4711)  
**Date:** 2007-10-25  
**Summary page:** https://www.summarizepaper.com/en/paper/0710.4711v1/

## Key points

- Introduces a novel FPGA architecture for implementing asynchronous logic
- Objective is to eliminate dependence between FPGA architecture and specific logic style
- Architecture is adaptable and has a generic structure for easy reconstruction and adaptation
- Practical demonstration of flexibility by implementing a full-adder using different logic styles
- Proposed FPGA architecture supports multiple logic styles without compromising performance or functionality
- Decoupling FPGA architecture from underlying logic style provides designers with greater freedom in design methodologies
- Contributes to advancing the field of FPGA design by promoting flexibility and adaptability in implementing asynchronous logic

## Summary

This paper introduces a novel FPGA architecture designed specifically for implementing various styles of asynchronous logic. The primary objective is to eliminate the dependence between the FPGA architecture and the specific logic style used. The authors describe the innovative aspects of this architecture, highlighting its adaptability and generic structure that allows for easy reconstruction and adaptation to accommodate future developments in asynchronous logic. The paper also presents a practical demonstration of the architecture's flexibility by implementing a full-adder using different styles of logic. This showcases how the proposed FPGA architecture can effectively support multiple logic styles without compromising performance or functionality. By decoupling the FPGA architecture from the underlying logic style, designers can enjoy greater freedom in choosing and evolving their preferred design methodologies. Overall, this research contributes to advancing the field of FPGA design by providing a new architectural framework that promotes flexibility and adaptability in implementing various styles of asynchronous logic.